Enhancing Drain Current Characteristic in Sub-10 nm Technology through p+ Pocket Negative Capacitance Double-Gate MOSFET

At transistor-level design minimizing dimensions and lower power consumption are the key parameters that have emerged as intense research topics. This paper presents the design of a p+ pocket Negative capacitance double gate MOSFET with a gate length of 10 nm with help of gate and channel engineering techniques to enhance subthreshold and ON/OFF performance. The double gate MOSFET stands out as a promising transistor option due to its enhanced subthreshold performance, making it particularly well-suited for low-power VLSI design. By employing an oxide layer of dielectric and coating of second oxide with ferroelectric material, can enhance the tunability of negative capacitance, significantly boosting the efficiency of FETs. The addition of a p+ pocket in the MOSFET structure further enhances the performance by modifying the channel properties and facilitating better control over the transistor’s operation also leads to improved barrier subthreshold conduction during the OFF-state of the transistor, while minimally impacting the ON-state current. The proposed device design and performance analysis are conducted through TCAD 2D/3D device simulation software developed by Cogenda.