A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory With Separated Source-Line

In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL). The proposed SSP scheme electrically separates the String-Select-Line (SSL) transistors to conduct program operations using the Bit-Line (BL) and SSL instead of BL and SL, thereby achieving low voltage and high-speed program operation. Since the proposed scheme is cutoff-based, it eliminates the necessity of high voltage (over 8 V) required for gate-induced-drain-leakage current generation in the inhibited strings, while effectively performing program operations in the selected string. To validate the proposed SSP scheme, we conducted TCAD simulations, the results of which show that the inhibited strings successfully operate even with voltages as low as 0.5 V and 2 V applied to the BL and SSL, respectively. In addition, the selected string consistently achieves high program speed regardless of the number of stacking layers. Therefore, the proposed SSP scheme is suitable for 3D NAND flash memory structures with separated SL, which require low voltage and high-speed programming.