Insights Into the Behavior of Leakage Current and Switching Instability in Lateral β-Ga₂O₃ MOSFETs

We investigate the performance of $\beta $ -Ga2O3 lateral MOSFETs on native $\beta $ -Ga2O3 substrates, featuring Fe ion implantation to address the known presence and the resulting effects of unintentional Si-impurities at the epilayer/substrate interface. A significant instability in threshold voltage (hysteresis) during ON/OFF switching, however, is still observed, which is attributed to traps inside the unintentionally doped (UID) buffer layer with an activation energy of $0.25 \; \pm \; 0.04$ eV, extracted using temperature-dependent current-voltage measurements complemented by with TCAD simulations. These trap states enhance the vertical conductivity of the UID buffer layer under high gate electrical fields, enabling charge flowthrough the secondary channel at the epitaxy substrate interface, if not perfectly compensated by the implanted Fe, with the vertical trap-enabled conduction path dominating leakage behavior of the device in the OFF-state. Our findings highlight the importance of considering not only the compensation of the Si impurities at the epilayer/substrate interfaces but also the role of traps inside the UID $\beta $ -Ga2O3 epilayer, after compensating the Si impurities by Fe implantation.