Accurate Charge-Domain Bootstrapped Computing-in-Memory SRAM Design with Wide Programmable Output Voltage Range

The computing-in-memory (CIM) architecture has been extensively employed in AI accelerators as a consequence of its energy-efficiency advantage in matrix-vector multiplication. Among various CIM architectures, the SRAM-based charge-domain CIM architecture is the focus of research due to the maturity of the SRAM process and the high energy efficiency of charge-domain analog computation. Nevertheless, charge-domain CIM arrays are constrained in output voltage range due to parasitic capacitance. In this paper, a charge-domain bootstrapped CIM SRAM with a wide programmable output range is provided. The proposed CIM SRAM array can compensate for the output range attenuation caused by parasitic capacitance, calibrate the output voltage curve and improve the computation accuracy. Evaluation results demonstrate that this work achieves a maximum 2 × output voltage range, and that the analog-to-digital converter (ADC) exhibits better quantization accuracy over a wider voltage range. In 28nm process, the proposed 128 × 128 SRAM array with 7-bit ADC has a reduced integral non-linearity (INL) range of 57.1%, a reduced differential non-linearity (DNL) range of 66.3%, and an improved signal-to-noise-distortion ratio (SNDR) of 8.18 dB.