System Design and Prototyping of the CMS Level-1 Calorimeter Trigger at the High-Luminosity LHC

The high-luminosity Large Hadron Collider (HL-LHC) proposes an ambitious physics program covering high-precision standard model (SM) measurements and advancing the searches for new physics. The efficient data gathering and precise events reconstruction in the intense environment of 200 proton-proton interactions per bunch-crossing (40 MHz) are essential for attaining the success of the HL-LHC program. To fulfill these requirements, the Compact Muon Solenoid (CMS) experiment is building entirely new data acquisition (DAQ) and trigger systems. The Phase-2 CMS Level-1 trigger system will drive the massive detector input data bandwidth of 75 Tb/s and is aimed to complete the single-event processing within $12.5 \; \mu $ s. For this purpose, the CMS plans to replace the Phase- $1 \; \mu $ Telecommunications Computing Architecture (TCA)-based processor cards and crates with an Advanced TCA (ATCA) specification. Each ATCA board is powered with a Xilinx UltraScale+ family field-programmable gate array (FPGA) that supports over 100 high-speed optical links at 25 Gb/s, capable of handling the high bandwidth and processing requirements of the HL-LHC. Along with the upgrade in hardware, the Level-1 trigger system will use highly flexible, modular, and adequately sophisticated algorithms currently feasible solely in offline reconstruction, such as a particle-flow (PF) algorithm. The flexible and modular architecture will assist in addressing the HL-LHC physics requirements. This article discusses the system design, prototyping, and algorithms being developed for the Phase-2 Level-1 Calorimeter trigger system.