Deep Neural Network Using Transfer Learning Technique for MOSFETs With Different Gate Lengths in Avalanche Region

In this paper, a transfer learning technique was first utilized to obtain deep neural network models for different gate lengths in the avalanche breakdown regime. Once the characteristics of a gate-length metal-oxide-semiconductor field-effect transistor are measured and the data are used to obtain a deep neural network, behavioral models for different gate lengths are established by fewer hidden layers and less measured data at the desired biases and frequencies. Therefore, the training data through this method is significantly reduced and the accuracy of the testing dataset is comparable to that of the conventional artificial neural network technique. The predicted, measured, and simulated results based on the transit time theory at different bias voltages and frequencies are in good agreement. Multibias S-parameter behavioral models in the breakdown regime can be efficiently built using this technique. This approach can even be applied to other advanced technology nodes and can shorten the model building time for CMOS circuit design operating in the saturation and avalanche breakdown regions.