Combined Reduction of DC-link Harmonics and Common Mode Voltage in Interleaved Multi-inverter Systems by Modified SVPWM Schemes

DC-link current harmonics and common mode voltage (CMV) are key design challenges for inverter-based power electronic systems. Addressing them collectively without additional hardware and/or complexity has promising advantages. This article investigates the interleaved utilization of modified space vector PWM schemes for parallel-inverter systems, targeting a combined and simultaneous reduction of these quality concerns. A time-domain analytical dc-link current formulation and a new application of sequence-based interleaving are combined in an offline numerical optimization algorithm that locates optimal interleaving shifts synced with the PWM sequence. With simulation and experimental validation, the corresponding numerical results ascertain an effective suppression of dc-link current harmonics alongside CMV reduction. In addition, this article extends the proposed idea to a special application for 3x multiphase machines through experimental validation.