First Simulation of the Effects of Metal Sidewall Source/Drain and Channel Number on the Output Characteristics of Current Mirror Formed by Vertically Stacked GAA Si NS MOSFETs

In this work, we study the effect of metal sidewall (MSW) sourceldrain (SID) on the circuit performance of current mirror (CM) formed by vertically stacked gate-all-around (GAA) nanosheet (NS) for the first time. Device DC characteristics and output current of CM with (wI) and without (w/o) MSW SID are explored by using an experimentally calibrated 3D numerical device-circuit simulation. Electrostatic potential distribution in the explored CM changes significantly because of serious parasitic resistance of SID. The CM wI MSW SID reduces the parasitic resistance of SID and has great influence on output characteristics relying on the channel number of GAA devices of the CM circuit.