Full Chip Stress Model for Defect Formation Risk Analysis in Multilayer Structures

To overcome the limitations of the previously developed stress simulation method for full-chip scale [1], which could only analyze a single layer of metallization due to its use of a shell element method, a simulation flow that can handle multiple layers was developed. Introducing stress simulation during the incremental formation of the back-end-of-line (BEOL) structure is crucial for predicting the risk of stress-induced defects not just on the surface, but throughout the entire 3D structure, including the chance of defects between metallization layers. To enhance the predictive capability for the larger-scale stress-induced defects, local stress averaging was utilized to balance simulation accuracy with coverage area. This methodology allowed for the expansion of the simulation domain beyond the chip level, thereby enabling the estimation of layout-induced deformations on a wafer scale