Utilizing Symmetric BSIM-SOI SPICE Model for Dynamically Depleted RF SOI T/R Switches and Logic Circuits

In this paper, we present the symmetric BSIM-SOI compact model, specifically designed for Dynamically Depleted Silicon-on-Insulator (DDSOI) MOSFETs, with an emphasis on optimizing their performance in RF Transmit/Receive (T/R) switch applications. This surface potential-based model provides a comprehensive characterization of the device’s behavior, covering both Partial Depletion (PD), Full Depletion (FD), and a smooth transition between PD-FD operational regimes, i.e., Dynamic Depletion (DD), while maintaining source-drain symmetry around $V_{\mathrm { ds}} = 0$ , thereby ensuring an accurate description of higher-order harmonics. The model has been rigorously analyzed and validated incorporating AC, DC, and RF characteristics with correlation to measured hardware data. Additionally, a description of the parasitic capacitances and resistances significant in determining the RF T/R switch performance is provided. Experimental validation was carried out using an advanced Single-Pole Single-Throw (SPST) RF T/R switch from GlobalFoundries Inc., with a thorough evaluation of key parameters such as on-resistance, off-capacitance, insertion loss, and isolation, including their frequency and temperature dependencies. Furthermore, a 65-stage ring oscillator performance was validated through the symmetric BSIMSOI model, demonstrating its effectiveness in logic applications as well.