Design of 32 Bit RISC V Processor

This paper presents the design and implementation of a RISC-V processor core with a single-stage architecture, focusing on the execution of the base 32I instruction set. The processor core features a 32-bit address and data architecture, with 32 general-purpose registers for data manipulation. The design adheres strictly to the RISC-V ISA specifications, ensuring compatibility with existing software and toolchains. Key components of the processor core include a fetch unit, decode unit, ALU unit, register file, memory control unit, and instruction memory unit. Through rigorous design and simulation, the processor core achieves single-clock-cycle execution, enabling efficient processing of instructions at an operating frequency of 2.2 KHz. The instruction memory unit facilitates the retrieval of instructions from a 4.5 KB memory array, while simultaneous read and write capabilities are supported for both registers and data memory. Additionally, 13 pseudo-instructions have been incorporated to enhance programming ease and readability. Performance evaluation of the processor core demonstrates its effectiveness in executing a variety of computational tasks, showcasing its reliability and efficiency within the specified operational parameters. The design serves as a foundation for future enhancements, including the integration of pipeline architecture, branch prediction mechanisms, and frequency optimization.