An Area-Efficient VLSI Architecture with Ladner-Fischer PPA for High-Speed Pseudo-Random Bit Generation

Pseudorandom Bit Generation (PRBG) plays a crucial role in ensuring the security of cryptographic systems by generating random bit sequences using deterministic algorithms. The effectiveness of these systems hinges on the unpredictability of the cryptographic keys they generate. This study focuses on optimizing the efficiency of PRBG systems by addressing key factors such as speed, area utilization, and power consumption. Leveraging the parallel prefix adder (PPA) architecture, particularly the Laden-Fisher design, our proposed method aims to enhance the performance of PRBG implementations. We present a Verilog-based design implemented using Vivado 2023.1 targeting an Artix-7 FPGA platform. Through this approach, we achieve rapid and reliable bit generation while effectively managing FPGA resources, ultimately enhancing the overall efficiency of PRBG systems.