Dynamic Input Pruning-Based Low-Power and Error-Optimized Approximate Adder

This paper proposes a new low-power and error-optimized approximate adder that leverages the dynamic input pruning technique and a reduced bit width adder. Traditional Ripple Carry Adder and Carry Look-ahead Adder suffer from large delays and high power consumption, respectively, particularly in applications where accuracy can be traded off for performance. The proposed dynamic input pruning technique carefully selects significant bits from input operands and passes them to a reduced-width exact adder, thereby shortening the critical path and improving performance metrics such as power consumption, delay, and accuracy. The design is implemented using Verilog-HDL on an Artix-7 FPGA platform in Xilinx Vivado EDA tool, enabling efficient hardware realization and evaluation. Experimental results demonstrate 36% reductions in dynamic power consumption and 9.6% shorter path delay compared to conventional adder while improving error metrics up to 47% compared to the state-of-the-art approximate adder. A trade-off analysis confirms the effectiveness of the proposed adder with available approximate adders.