Design of Low Power CMOS based Array Multiplier in 90nm Technology

Power-Dissipation, latency, layout, and power-delay product are the key considerations in circuit design in nanometer technology. Multiplication is the basic arithmetic unit in DSP applications and embedded systems. Multiplication is the repeated process of addition. By optimizing the structure of adders in the multiplier, one can have improvements in terms of power, latency, area, and power-delay product. In this paper, a low-power array multiplier and the conventional multiplier are designed by optimizing the Full adder structure. A 14-T Full adder circuit is designed using XOR and MUX logic functions. Each XOR and MUX logic function is designed using 2 transistors. Extra two transistors are added at each output sum and carry to obtain full swing at output voltages. An array multiplier using the proposed full adder can be used best when power is a major requirement. Array multiplier with proposed full adder shows power dissipation of $38.59 \mu \mathrm{~W}$ and delay of 0.182 ns at a supply voltage of 1.2 V.