Design and Verification of a Cache Coherency Verification IP for AMBA ACE Protocol Using UVM

The ever evolving architecture of SoCs has created the need for a robust communication protocol to maintain the data consistency and data integrity between multi-master SOCs. This obstacle has been overcome by the AMBA ACE protocol. In the proposed Verification IP, the AMBA ACE protocol has been verified with the help of a write-through, two-way set associative cache which has the cache line size of 32 Bytes, supports both read and write allocate. The VIP has been verified in three different phases defined as read phase, write phase and snoop phase. The simulation of the implementation was completed in Cadence Xcelium Logic Simulator tool.