FPGA Implementation of XOR-MUX based Full Adder and Truncated Multiplier for Signal Processing Applications

There has been considerable advancement in the digital world, particularly in image processing applications, in recent years. The most important requirements are area efficiency, minimal delay, low power consumption, and fast speed. Due to the arithmetic operations of adders and multipliers, digital devices are prone to have increase in the size of logic because they take up more space in VLSI implementation. The proposed method of XOR-MUX based full adder and truncated multiplier concentrates on reducing the delay and area. Replacing normal multipliers with truncated multipliers computes $\mathbf{n}$ bit output instead of $2 \mathbf{n}$ bit outputs that is, the MSB bit of the truncated multiplier are retained whereas the LSB bits are truncated thereby preserving the information. This is suitable for certain applications of FIR filters that do not concentrate on lower bit length. In this project, the conventional full adders are replaced by XOR-MUX based full adders and are utilized in truncated multipliers which results in area reduction by 12.66% and delay reduction by 11.68% with a modest increase in power consumption. This reduction in truncated multipliers contributes towards the design of high performance FIR filters in signal processing applications.