A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoM $_{\mathrm{w}}$ Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver

This article presents a 1.75-GS/s single-channel 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) that is based on loop-unrolled architecture with N-comparators for N-bits. A memory-less fully asynchronous SAR is proposed to lower power consumption and reduce design complexity. A double-tail feed-backward (DTFB) dynamic comparator is proposed to meet the required speed and minimize thermal noise, which is a critical parameter for a 7-bit SAR ADC. The prototype ADC is implemented in a 3-nm CMOS process. The ADC achieves an SNDR/SFDR of 37/49 dB at Nyquist, 0.00055-mm
$^{\text{2}}$
area, and consumes 0.69-mW power. This leads to a best-in-class Walden figure of merit (FoM
$_{\mathbf{w}}$
) of 6.9 fJ/conv.-step and a Schreier FoM of 158 dB at Nyquist. This SAR ADC is used in a 64-way time-interleaved (TI) ADC to achieve 112-GS/s operation for use in an ADC-based 224-Gb/s PAM4 SerDes receiver.