Self-Heating Effect Analysis and Characterization of 6T SRAM Based on Delay Variation

With the introduction of FinFET transistors, the self-heating effect (SHE) became a major reliability challenge. This leads to accelerated defect generation and, if not considered carefully, a profound risk to integrated circuit (IC) reliability. In this article, simulation is used to analyze the SHE of 6T static random access memory (SRAM) based on 14-nm FinFET, providing a basis for the thermal layout of 6T SRAM in circuit design. The impact of SHE on 6T SRAM is analyzed. For the first time, it is proposed that the reading delay time with the change of duty cycle shows a rising and falling trend, which is further verified by using simulation, theoretical analysis, and field-programmable gate array (FPGA) experiments. Thus, the duty cycle and read delay time are utilized to achieve binary encoding for the characterization of the SHE of 6T SRAM. The results indicate that the method can be used to characterize the ${T}_{\text {SHE,max}}$ (the highest ${T}_{\text {SHE}}$ among six transistors) range: 0 °C–84.5 °C, with a ${T}_{\text {SHE,circuit}}$ (representing ${T}_{\text {SHE}}$ of the 6T SRAM) range: 0 °C–48.8 °C. The characterization method enables the practical measurement of SHE in circuits based on 6T SRAM technology, which is no longer limited to existing transistor simulation and modeling methods, allowing for more precise testing of circuit reliability. At the same time, it eliminates the need for additional thermal sensing circuits and testing equipment.