An Optimised Design of a 4-bit Carry Look-Ahead Adder Using Novel Reversible Logic Gates

Reversible logic gates are pivotal in the advancement of low-power and quantum computing technologies due to their ability to operate without generating heat from information loss. This field of study has emerged as a forefront of research, propelling innovative advancements aimed at optimizing resource efficiency. This paper presents the design and implementation of a 4-bit Carry Look-Ahead (CLA) adder using reversible logic gates, significantly enhancing arithmetic operation speed by computing carry bits in parallel. The CLA adder uses generate (Gi) and propagate (Pi) functions to determine carry bits, reducing the delay associated with traditional adders. The proposed design leverages a combination of Peres and Feynman gates to construct the Carry Propagate and Carry Generate Adder (PGA) block, producing the necessary carry and sum outputs efficiently. There is an approximate 41% improvement in the total reversible implementation cost (TRLIC) of the design. Evaluated using Vivado 2022.2 with Verilog HDL, the design demonstrates accurate and efficient performance across all 4-bit input combinations, significantly reducing propagation delay.