Integrated single-stage column AFE for CMOS image sensor single slope ADCs

The paper presents analog and dual correlated double sampling (CDS) stages employed in single-slope analog-to-digital converters (SS-ADC). The converter front-end comprises a single operational amplifier with switch-capacitor periphery circuitry. The compact architecture can perform operations such as CDS, auto-zeroing, amplification with programmable gain (PGA), and comparison that are combined as analog front end (AFE). Both CDS implementations are described in a system that uses only analog CDS for high-speed imagers and another structure for low-noise CIS applications. Due to the constantly increasing resolution of CMOS image sensors, the demand for high-integrity column-parallel ADC requires compact design solutions. The proposed concept is design-completed and simulated data supports the system validity provided along.