A 7.2G-16GHz ADPLL based on a single-core dual-mode DCO

This work proposed a 75.9% wide frequency tuning range (FTR), low-jitter All Digital Phase Locked Loop (ADPLL) based on a new single-core dual-mode digital controlled oscillator (DCO). The two modes of DCO consisted of Parallel-Mode and Series-Mode, demonstrating continuous frequency tuning from 6.76 GHz to 16.29 GHz. The coefficient of mutual inductance (k) requirement of the resonant tank was flexible and the implementation was high-frequency friendly. Fabricated in a 40 nm-CMOS process, the proposed ADPLL had a frequency tuning range from 7.2 GHz to 16 GHz. The power consumption was 18.9 mW and the active chip area was 0.18 mm. The RMS jitter spanned from 91.65 fs to $\mathbf{1 0 3. 8 f s}$. The corresponding figure-of-merit tuning $\left(\mathrm{FoM}_{T}\right)$ was -246.8 $\mathrm{dB} /-245.7 \mathrm{~dB}$.