A 13b 40MS/s SAR ADC with Robust kT/C Noise Cancellation using a Feedback Auxiliary Amplifier

This paper presents a 13b 40MS/s SAR ADC with a robust $\mathrm{kT} / \mathrm{C}$ noise cancellation technique, which cancels the $\mathrm{kT} / \mathrm{C}$ noise by forming negative feedback with an auxiliary amplifier, thereby making the noisy node to virtual ground. After kT/C noise cancellation, an independent SAR operation is performed with a kT/C noise-free signal. Since the auxiliary amplifier is only used at the end of the sampling phase, a duty-cycled amplifier is used, resulting in low power consumption. This work achieves the suppressed $\mathrm{kT} / \mathrm{C}$ noise with a sampling capacitor of 128 fF, which is equal to the $\mathrm{kT} / \mathrm{C}$ noise level with a 2 pF sampling capacitor. Fabricated in a 65 nm CMOS process, the prototype ADC achieves a DR of 69.7 dB, a SNDR of 68.5 dB while consuming only $667 \mu \mathrm{~W}$ from a 1.2 V supply. These results are verified with 3 samples under $\pm 20 \%$ variations in the supply voltage. It results in very competitive FoMs: a FoM $M_{D R}$ of 174.5 dB and a FoMw of 9.4fJ/conv.-step.