An 8 GHz 9 bit Phase-Rotating ILCM with DTC Range Reduction for High-Speed Serial Links

This paper presents a phase-rotating injection-locked clock multiplier (PR-ILCM) for clock and data recovery, especially suitable for multi-lane high-speed sub-rate receiver (RX) architecture. The proposed PR-ILCM performs frequency multiplication, multi-phase generation, and infinite phase shift simultaneously, eliminating the need for high-frequency global clock distribution, local quadrature phase generation, and multiple PIs, thereby saving clocking power significantly. PR-ILCM employs a single DTC and low-power simple rollover code search logic for seamless phase rotation. Fabricated in a 28 nm CMOS process, the prototype 2-lane 16 Gbps/lane RX with the proposed PR-ICLM achieves 1.9 pJ/bit energy efficiency, which greatly improves that of conventional multi-lane RX architecture with high-frequency clock distribution. Generating 8 GHz 4-phase clocks, PR-ILCM also shows better resolution (9 bits) and linearity (0.54 LSB DNL, 1.34 LSB INL) than previous phase-rotating multi-phase generators.