A 0.0102mm2 4.62nW Process-Skew and Temperature Compensated Current Reference Operating from –40°C to 125°C with 297ppm/°C

This paper presents a current reference consuming 4.62 nW at 0.5 V with an active area of $0.0102 \mathrm{~mm}^{2}$ in $0.18 \mu \mathrm{m}$ standard CMOS technology. Iref is generated by applying PVT invariant voltage across a temperature-compensated resistor. The proposed design achieves the applied voltage below 5 mV by using a self-cascode configuration and improves the trade-off relationship between power and area while maintaining the PVT variation of the previous resistor-based $I_{\text {REF }}$ generation. $I_{\text {REF }}$ from 10 chips shows a level of 4.2 nA, a temperature coefficient (TC) of 297ppm $/{ }^{\circ} \mathrm{C}$ from $-40^{\circ} \mathrm{C}$ to $125^{\circ} \mathrm{C}$, and a line sensitivity of $0.27 \% / \mathrm{V}$ from 0.5 V to 2 V.