A 22nm 9.51 TOPS/W Neural Engine with 2MB MRAM Leveraging Sparse-Orthogonal Walsh-Hadamard Transform Computations and Dynamic Power Gating

We present the first silicon implementation of a Walsh-Hadamard transform based neural network (WHT-NN) processor featuring 2MB MRAM for all-on-chip weight storage, targeting edge devices. The design overcomes the high leak-age and access time of MRAM with several schemes such as dynamic power gating and multi-clock domain double-buffered caching. Our processor demonstrates best-in-class 9.51 and 22.86 TOPS/W peak energy efficiencies for sparse convolution and fully-connected layers, respectively, in 22 nm CMOS.