A Reconfigurable SAR ADC Based on Nested Quantized-Analog Sample and Hold

Quantized-Analog signal processing technique is applied to a time interleaved SAR ADC by increasing resolution, resilience to mismatches, and power efficiency. The SAR driver is quantized in a nested fashion. One layer of QA is used to increase the overall full scale of the ADC leading to 8 dB increment of the SNDR while doubling the power efficiency. A second layer is used to enable an agile calibration of the SAR. The results is a reconfigurable ADC with maximum 8.9-bit ENOB at 2 GS/s and FOM of 155.2 dB.