Low-frequency Noise Performance of pMOS SOI Transistors for Analog Applications

This work assesses the low frequency noise level behavior for mesa isolated silicon-on-insulator (SOI) pMOS transistors dedicated to analog applications. Noise scaling with gate design, including gate length and gate width, is firstly studied. It demonstrates a nominal noise scaling with gate dimensions, even at small surfaces. Technological variants are then introduced, with forming gas anneal and source/drain engineering influence. On this technology our results demonstrate that forming gas anneal is efficient to reduce low frequency noise. The pMOS SOI transistor noise performance is finally compared to literature, illustrating promising noise figure of these devices isolated by mesa process.