A Novel CMOS FEOL-Embedded Asymmetrical FET for Capacitor-less and Long-Retention DRAM Based on 300mm Logic Foundry Platform

For the first time, a novel CMOS-compatible and capacitor-less Asymmetric FET (AsyFET)-based 2T0C DRAM with significantly enhanced retention is proposed and experimentally demonstrated based on standard 300 mm logic foundry platform. Without area penalty or new materials, the fabricated Si AsyFET can obtain ultralow off-state current of $\sim 10^{-17} \mathrm{~A} / \mu \mathrm{m}$, leading to the long retention of 3.9 s in 55 nm technology node. In AsyFET, the modulated Schottky direct tunneling current and band-to-band tunneling current are designed to write “ 1 “ and “ 0 “ respectively without write disturb, and show negligible temperature dependence on write speed of below 5ns. Benefiting from the monolithic integrated process, standard MOSFET can be used as the read transistor of AsyFET 2T0C DRAM for fast read, and the Vsn enhancement design enables larger storage node voltage for long retention and large memory window. The experimental results show the great potential of proposed AsyFET 2T0C DRAM design for low-power, high-density, and high-speed onchip memory.