Modified Flip Flop with Two Phase Clocking for Low Power Consumption

This paper proposes a modification in the clocking scheme, which aims at reducing the power consumption by implementing the circuit using two-phase clocking, that is an improved version of single phase clocking. Employing the two-phase technique, known for its effectiveness in tackling issues like clock skew and race conditions seen in single-phase clocking, this method achieves a significant reduction in power consumption. Implemented on 100 nm CMOS technology using the Cadence Virtuoso tool, this approach demonstrates better results, with power reductions of approximately 6.16% and 23.24% observed at 1V and 0.6V power supplies, respectively. These results signify the circuit’s effectiveness in minimizing power consumption for contemporary integrated circuits.