Parallel Prefix Adders Based Linear Congruential Generator

In cryptography pseudo-random generators play a key role; to generate these random bits linear congruential generator is implemented with different parallel prefix adders to increase the speed of operation. LCG module consists of a shifter, adder, multiplexer, and register. In parallel prefix adders, the operation is performed in parallel by dividing into smaller pieces that are done in parallel. To further reduce the number of grey cells and black cells Ladner-Fischer adder is implemented for further reduction in the proposed LCG. In the place of the adder is replaced with different adder structures and is verified with different FPGA families for the utilization and timing report. The architecture is implemented using Verilog HDL, simulated, and synthesized using Vivado.