A 50 Gb/s PAM-4 Transceiver With High-Swing Driver, Dual-Loop Analog Equalizer, and Integrator-Based Baud-Rate Linear CDR for Short-Reach Links

This paper presents a 50 Gb/s four-level pulse amplitude modulation 4 (PAM-4) wireline transceiver that incorporates a high-swing PAM-4 driver in the transmitter (TX) and an integrator-based baud-rate linear clock and data recovery (IB-CDR) in the receiver (RX). The PAM-4 driver in the TX employs two types of non-return to zero (NRZ)-current mode logic (CML) drivers. The proposed architecture overcomes the inherent signal-to-noise ratio (SNR) limitations of PAM-4 by generating signal amplitudes greater than the supply voltage (VDD). The RX features an IB-CDR that can determine the phase difference between the PAM-4 signal and the sampling clock using the sign and magnitude of the integrators. Consequently, because the IB-CDR can reduce the requirement for additional threshold voltages and samplers for CDR operation, the RX can achieve a competitive Figure-of-Merit with reduced hardware overhead. Moreover, a dual-loop analog equalizer (DAEQ) is introduced to mitigate inter-symbol interference between the TX and RX. In the DAEQ, one loop increases the peak gain, while another loop controls the system bandwidth. The proposed TX and RX were fabricated using a 28 nm CMOS technology and has a maximum data rate of 50 Gb/s. The prototype with a total area of 0.18 mm2 enables a bit error rate of $10^{-11}$ at 15.3 dB attenuation and has a power efficiency of 3.28 pJ/bit.