Development of Low Power Energy Efficient 32nm SRAM Utilizing Sleep Transistor Technology

In data processing, RAM (Random Access Memory) is essential for faster applications in various computing systems. SRAM (Static Random Access Memory) has high speed and faster operations when compared to DRAM (Dynamic Random Access Memory). SRAM is intended to replace DRAMs in systems with deficient power consumption. It aims to have a direct interface with the CPU (Central Processing Unit) at speeds impossible with DRAM. The research aims to design a low-power energy-efficient SRAM cell in 32nm using sleep transistor logic. The process entails integrating sleep transistors which acting as a switch to cut off specific circuit blocks from the power source when they are not actively processing data. When the power supply to a SRAM cell is interrupted, it continues for subsequent memory access to store the high-speed data frequently instead of data refresh. The method incorporates CMOS (Complementary Metal-Oxide-Semiconductor) technology to design a variety of SRAM cells with 10T, 9T, 8T, 7T, and 6T configurations with sleep transistor logic in 180nm, 90nm, 65nm, 45nm, and 32nm. A sleep transistor is mainly employed to achieve low power consumption using leakage reduction. The research also aims to increase read and write stability while reducing power consumption. Sleep transistors facilitate improved power management by efficiently putting memory cells into a low- power sleep mode when not actively used. Comparing all the methods, the proposed 32nm 6T and 4T Sleep SRAM cells have improved power, energy, and delay by 10-40%, 9-18%, and 70- 90% respectively.