Implementation of High-Speed Full Adder Using XOR XNOR Cell in FinFET Technology

In most electronic devices, arithmetic circuits play a significant role, with adders serving as fundamental components. When it comes to designing a full adder circuit, various approaches are available. However, our preference is to create circuits that are both high-speed and energy-efficient. Traditional designs, consisting of 28 transistors, tend to hinder circuit speed. Therefore, we propose a hybrid design style aimed at enhancing speed and reducing power consumption. This proposed system incorporates only 10 transistors and includes a XOR-XNOR circuit, contributing to the development of a full adder that is both energy-efficient and high-speed. The design is implemented using Cadence with FinFET technology(GPDK 18nm technology) in the Virtuoso tool, resulting in a reduction in the Power Delay Product (PDP) and an overall improvement in system performance.