Modeling the Impact of Interface and Border Traps on Hysteresis in Encapsulated Monolayer MoS2 Based Double Gated FETs

Observable hysteresis in the transfer characteristics of two-dimensional (2-D) based FETs pose a roadblock in realizing reliable 2-D CMOS integrated circuits and requires precise physics-based understanding. Therefore, we investigate the impact of interface and border traps on the threshold voltage hysteresis using a drift-diffusion (DD) based TCAD simulation framework. Theoretically, the fast interface traps and the slow border traps cause a shift in the hysteresis profile when measured across a wide range of gate voltage sweeping frequencies. Accurate modeling of these traps is thus required to fully capture their dynamics and impact on reliability. The limited range of possible gate voltage sweeping frequencies in an experimental set-up might not be sufficient to fully capture the nature of the hysteresis. For instance, the peak of the hysteresis profile might lie outside the experimental window. Therefore, in this study, we theoretically investigate the dynamics of interface and border traps and their impact on the reliability of 2-D FETs across a wide range of gate voltage sweeping frequencies to determine their key properties.