Hybrid CMOS Memristor Based Frequency Divider Using D Flip Flop

Memristors' ease of integration with contemporary CMOS technology has led to their widespread use in the design of logic circuits in recent years. Consequently, the development of hybrid memristor CMOS logic circuits has led to a reduction in the power consumption, device area requirements, and additional latency of logic circuits. In this study, a hybrid memristor CMOS logic frequency divider is created as a basic clock divider to split the frequency of another signal. By importing its SPICE model and TSMC 180nm model files into LTSPICE, the Knowm memristor is used to build and simulate the critical blocks, which are the NOR gate-based D Flip-Flops. Moreover, the recommended designs use fewer components, resulting in greater space efficiency and potential for complex circuit design and execution.