Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs

The layout area and power consumption of a charge-scaling digital-to-analog converter (DAC) is typically dominated by the capacitor array. For a binary-weighted DAC, since the number of unit capacitors in the array increases exponentially with the number of bits, minimizing the size of the unit capacitor is crucial for controlling the layout area. A split DAC uses many fewer unit capacitors than the binary-weighted DAC, but requires the use of noninteger multiples of a unit capacitance; the choice of unit capacitor remains an important consideration. Smaller capacitors can be susceptible to larger amounts of noise and process mismatch, and can also be affected by mismatch in the parasitics of routing wires that connect the capacitors in the array: the latter is particularly significant in FinFET nodes. Together, these factors can degrade critical DAC performance metrics unless the unit capacitor is sufficiently large. This work proposes a systematic approach for selecting the unit capacitance value in both binary-weighted and split capacitor arrays for charge-scaling DACs. The proposed method selects a value that optimizes the nonlinearity metrics of a DAC, accounting for multiple factors that contribute to mismatch, flicker noise, and thermal noise. Our results demonstrate that by using a systematic methodology to size the unit capacitor, it is possible to overcome shifts due to process variation and noise for 6-bit to 14-bit DACs. Particularly for higher-resolution DACs, it is seen that the minimum unit capacitor value for binary-weighted DACs is lower than for split DACs, but the former incurs much larger area costs since it contains a significantly larger number of unit capacitors.