Surface-Potential-Based Drain Current Model of Gate-All-Around Tunneling FETs

A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated. Foremost, the correctness of the dual modulation effect in GAA-TFETs is demonstrated. Building on that, the model comprehensively considers the effects of the channel depletion region, drain depletion region, and channel inversion charges. Furthermore, a compact current model for GAA-TFETs, based on the derived surface potential expression, is presented, with a discussion on ambipolar conduction—an essential factor for device model integrity. The model’s accuracy and flexibility are validated through TCAD simulations and measurement data from NW-GAA-TFETs, yielding promising results.