A Digital SRAM-Based Computing-in-Memory Macro Supporting Parallel Maintaining for Network Management

A digital SRAM-based computing-in-memory (CIM) macro is proposed to enable parallel maintaining for statistics counters in network management. A new 18-transistor bit-cell is designed to support in-situ counter maintaining. A joint coding scheme and a daisy-chain circuit are leveraged to enhance the throughput as well as reduce the computing energy consumption and area. The proposed CIM macro saves $6.9\times $ in energy at 1.2 V and $2.33\times $ in area compared with the conventional statistics counters in a 55-nm CMOS technology.