Sneak Circuit Analysis of Relay Circuits Based on Logic Delay Petri Nets

Sneak circuit analysis is a vital component of circuit reliability assessment. However, conventional methods for sneak circuit analysis are unsuitable for relay circuits. In this paper, we propose an innovative method for analyzing sneak circuits in relay circuits based on logical delay Petri nets (LDPNs). Based on logic Petri nets, we construct the LDPNs by introducing temporal properties and provide a formal description of relay circuits. Subsequently, rules for abstracting relay circuits as directed graphs and rules for constructing LDPN models are proposed. Employing a railway relay interlocking system as a case study, a relay circuit execution simulation algorithm is proposed based on the evolution principle of LDPNs. This circuit is used to simulate the execution process and final response of the relay circuit under specified excitations. The algorithm facilitates the detection of all pathways during circuit execution, enabling the detection of sneak circuits. Consequently, our proposed methodology can significantly enhance circuit reliability.