Signal Integrity Optimization for CoWoS Chiplet Interconnection Design Assisted by Reinforcement Learning

In this work, a deep reinforcement learning (RL)-based model was developed to design optimum signal/ground line arrangements in CoWoS (i.e., chip-on-wafer-on-substrate) technology for chiplet heterogeneous integration while improving signal integrity design. The proposed method addresses the difficulties of expansive design space exploration and offers efficient design optimization. The RL model can find the optimal combinations of signal/ground line geometry parameters and arrangements for high data rate, which can meet the performance requirements indicated in Universal Chiplet Interconnect Express (UCIe) specification in terms of eye diagram, and voltage transfer function (VFT). The framework can mitigate the crosstalk of high-speed data transmission, improve signal quality, maximize signal density, and reduce design time for engineers.