Improving the Wafer Thinning Flow Robustness for 2.5D & 3D Applications

Packaging technologies (2.5D, 3D) require the thinning of device wafers, down to sub 100 µm in thickness. While using a temporary carrier for that purpose has become, today, a very common approach from a “process integration” perspective, such process might suffer from a reduced wafer Yield though, because of edge chipping. The bonding misalignment and the TBM edge-bead removal (EBR) width variations have been identified as the main contributors to edge chipping, and included as variables, in a statistical model. This helped drive the design of experiments and tune the existing process flow. Increasing the edge trim width from 500μm to 1mm proved to be very effective in decreasing the edge chipping occurrence, while inducing no negative effects on the downstream thinning flow.