A Hardware Architecture Design for High-Speed Vessel Orientation Recognition

Vascular orientation recognition (VOR) holds widespread applications in biomedical domains such as vascular image processing. Although many methods based on deep learning (DL) running on CPUs have been proposed and achieved appreciable results, they encounter a speed bottleneck. Therefore, an FPGA-based hardware design scheme is proposed in this paper to achieve high-speed VOR using small circuits. The design employs a streaming processing method for image thresholding and replaces static lookup tables (LUT) with the CORDIC algorithm to reduce resource consumption. Additionally, further compression of the angle mapping range is employed to achieve superior hardware resource optimization. Compared to purely software solutions, experimental results obtained with the simulated and actual vascular images demonstrate a 12.9x computational acceleration employing the proposed scheme. Moreover, the proposed scheme, in contrast to hardware implementations based on Lookup Table and Function Approximation, reduces LUT resource consumption by over 60%. Compared with two previous CORDIC algorithm studies, the proposed algorithm achieves a 14.6% and 20.5% reduction in LUT resource usage, thus showing enormous potential in real-time medical devices for tracking and computation of main vascular trajectory.