High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA

In recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs). Tapped delay-lines (TDLs) are simple to implement but require careful design decisions for high precision and linearity. Although various implementation strategies have been explored in TDC literature across different FPGA technology nodes, the 16-nm node has only recently begun to receive attention. The goal of this study is to leverage a 16-nm FPGA for TDL-TDCs with the requirement of maintaining implementation simplicity while ensuring top-tier performance. We investigated, combined, and optimized various state-of-the-art TDL techniques using an AMD-Xilinx Zynq Ultrascale+ RFSoC. The 16-nm node offers logic buffers (CARRY8) with low propagation delay, ideal for the construction of TDLs. We designed multi-channel TDCs utilizing both single and multiple carry chain TDLs. Propagating a single signal edge allows the use of a simple, bubble-free ones-counting encoder. Buffer redundancy subdivides the bins of the code density histogram, whose linearity is further enhanced by bin decimation. The optimal placement of the TDL elements is considered, together with the sampling clock frequency and source. We demonstrate the capabilities of the TDCs in terms of full-scale range (FSR), dead time, nominal resolution (LSB), RMS precision, differential and integral nonlinearity, hardware utilization, and power consumption. This method leads to TDCs that are simple to implement yet excel in performance, linearity, and sampling rate. For example, we propose a 4-chain TDC achieving LSB < 4 ps, single shot precision (SSP) < 3 ps, DNL < 1 LSB and INL < 2 LSB.