Assessing NI FPGA-based platform with MXIe interface for use in ITER hard real-time investment protection applications

The ITER Interlock Control System (ICS) assumes a crucial role in the tokamak operation to protect the investment against machine protection hazards. Consequently, it must be developed in compliance with the most challenging requirements. The National Instruments CompactRIO (NI cRIO) technology was chosen by ITER as the Field Programmable Gate Array (FPGA)-based platform to develop the investment protection functions, with strict time-constraints. This contribution focuses on the specific requirements for the ITER Advanced Protection System (APS) where the disruption mitigation control function requires a sequenced release of hydrogen ice pellets with an accuracy of less than 1ms. These requirements are an evolution of previous protection system designs based on cRIO and motivated this feasibility study. The cRIO platform used at ITER is the NI9159, which provides an MXIe interface between a Virtex 5 LX110 FPGA and a host computer running a Linux preemptive kernel. ITER decided to improve two important requirements: the MXIe interface communication latency’s jitter by redesigning the ITER NI-RIO Linux device driver; and the ability to timestamp events in the FPGA logic by designing a specific firmware module based on the Precision Time Protocol as used in the ITER Time Communication Network (TCN). This contribution reports the design methodology followed, the firmware and software elements implemented, and the time-keeping performance obtained of the approach.