A Scan-Chain-Based Built-in Self-Test for ILV in Monolithic 3-D ICs

In comparison with through-silicon vias (TSVs) used in 3-D integrated circuits (3D ICs), nanoscale interlayer via (ILV) employed in monolithic 3D ICs offers higher integration density. However, the elevated integration density, coupled with the corrosive scaling of interlayer dielectric (ILD) and immature manufacturing processes, can lead to failures in ILVs. Built-in self-test (BIST) can be used to test and diagnose ILVs. Previous research on ILVs in monolithic 3D ICs assumed 1-D (
$1\times $
D) placement and limited bridging faults (shorts) occurring only between ILVs in the same direction. However, to minimize the wiring length in monolithic 3-D (M3D), the layout of ILVs may adopt an irregular arrangement, and at the same time, bridging faults may occur between ILVs in different orientations. To detect and locate all possible ILV faults in a real ILV layout, a new BIST method is proposed, which can detect open, stuck-at faults (SAFs), and all possible shorts in ILVs by using the scan chain encapsulated in the active layer. The simulation results using HSPICE and Vivado show that the proposed BIST method can effectively detect and locate faulty ILVs.