Low Latency VLSI Architecture of Histogram Equalization of Images

Histogram is an important feature of the digital images used in many image transformations. This paper proposes an efficient VLSI architecture of histogram generation and equalization of the images with the range of pixel values from 0 to 255. In our proposed design, the delay is reduced as compared with various existing designs. We have eliminated the requirement of histogram storage unit. However, the temporal buffers are introduced in our proposed designs to store the histogram along with the pipelined divider unit. It lowers the critical path delay of the proposed design. All the existing and proposed architectures are implemented with 45 nm CMOS technology. The synthesis results reveal that, for the implementation of (22 × 23)-point grey image, the proposed architecture of histogram equalization lowers the delay by 83% and 85%, respectively, in comparison to the current designs as shown in [13] and [14].