Design and ASIC Implementation of Area Efficient UART Core in SCL 180nm Technology

In this paper, we present the design and implementation of an 8-bit Universal Asynchronous Receiver-Transmitter (UART) operating at a baud rate of 9600. Our objective was to develop a UART design optimized for minimal area and power consumption, achieving an area of 7005.740 µm² and a power consumption of 506.108 µW. The design process was comprehensive, covering the entire flow from RTL to GDSII. This thorough execution ensured robust performance and efficient integration into larger systems. A key aspect of our design is the inclusion of input/output (I/O) padding, enhancing signal integrity and facilitating seamless integration with external components. This feature is crucial for maintaining reliable data transmission, especially in environments with potential signal interference. Our methodology effectively balances power efficiency and area optimization, making the UART design suitable for a wide range of applications in embedded systems and communication interfaces. The design was synthesized using the SCL180 technology library and the results demonstrated that our design consumes the least area while maintaining competitive power efficiency. Furthermore, the design was thoroughly verified through simulation in Xilinx Vivado, and the synthesis process was conducted using Cadence Genus. Floorplanning was performed in Cadence Innovus, and the final design was imported into Siemens Calibre for Design Rule Checking (DRC). These steps ensured the design adhered to fabrication standards and was ready for tape-out.