Runtime Prediction for VLSI Physical Design Processes using Machine Learning

Accurate runtime prediction is crucial in VLSI physical design processes to enhance resource management, scheduling, and overall project efficiency. This paper presents a methodology for predicting runtimes of floorplanning, placement, and routing phases using machine learning models. A comprehensive dataset was generated from 433 different VLSI designs using Cadence Genus and Innovus. Various machine learning algorithms, including linear regression, decision trees, and advanced ensemble methods such as gradient boosting, were evaluated to identify the most effective model. The Gradient Boosting Regressor demonstrated superior performance, achieving high R² scores and low RMSE values. By integrating these models into the VLSI design workflow, we can achieve significant improvements in runtime prediction accuracy. This approach not only enhances the efficiency of the design process but also reduces overall design time and costs. The findings suggest that machine learning can play a pivotal role in optimizing VLSI design workflows, paving the way for faster and more cost-effective development of advanced electronic devices.