Design, Validation and Characterization of Number Theoretic Transform IP Core

The Number Theoretic Transform (NTT) is a mathematical concept that solves complex problems in cryptography. It is recognized as a very efficient transform for the multiplication of two polynomials with high degrees, which have integer coefficients. It is widely used in practical implementations of cryptography schemes that are lattice-based. The NTT can be considered a variant of the Discrete Fourier Transform (DFT) that operates on integers. It deals with a ring of integers with the modulus of a prime number. The transform involves arithmetic in a modular approach, making it suitable for computations in a finite field. However, solutions implementing the NTT suffer from computational inefficiencies, limiting applications in various critical domains such as cryptography, signal processing, and arithmetic operations in finite fields. There is a need for an optimized hardware solution for the computation of the NTT in VLSI design. There are limitations on the modulus to be in a particular form. To address this gap, this work aims to design, validate, and characterize an Intellectual Property (IP) Core based on the NTT, catering to the need for specialized hardware that facilitates integration into diverse VLSI designs. The work has been carried out on the ARTY Artix-7 100T FPGA Development board with part number XC7A100TCSG324-1 with multiple inputs of different dimensions. RTL implementation of the Number Theoretic Transform has been done to verify the accuracy of the computation. Once it is found to be accurate, an IP core has been developed that meets the timing and power constraints. The performance metrics have been calculated for the characterization of the NTT IP core. The work has been carried out with two models of different dimensions. On-chip debugging with the FPGA is done on the created models to validate the NTT computations of given input sequences. It is observed that there are no limitations in the modulus or the twiddle factor for this design. Additionally, this design accounts for computational accuracy on the given inputs within the specified data limits.