Optimized Test Pattern Generation for Digital Circuits using SAT-Based ATPG and Scan Insertion Method

Testing is pivotal in ensuring the reliability and functionality of digital circuit. Generating specific test inputs or test vectors is essential for fault detection within the circuit. However, as digital circuits grow in complexity and size generating these inputs becomes increasingly challenging computationally. Test data volume and Test time are critical parameters impacting the efficiency of circuit testing. In the case of sequential circuits, the scan insertion approach streamlines testing by converting regular flip-flops into scan flip-flops using various EDA tools. Using the Scan DFT technique, sequential circuits were tested using Synopsys Tetramax and Fusion Compiler, resulting in a remarkable 80-95% reduction in total test time with the implementation of scan compression. To tackle this complexity in testing combinational circuits, we have used the Boolean Satisfiability (SAT) technique, leveraging PycoSAT solvers. This paper focuses on enhancing the efficiency of testing digital circuits by optimizing parameters like Test Time and Test data. Additionally, the test generation algorithm implemented using Python successfully identified equivalent faults for combinational circuits, leading to the acquisition of an optimized test set. To address the complexity of large combinational circuits, a preprocessing technique called clause subsumption elimination, in conjunction with Boolean Satisfiability (SAT), was utilized to generate test sets from extensive DIMACS files. This approach demonstrated a significant reduction in solving time when multiple faults were injected for various circuits.